Using Python to Create Tedious Verilog Code

The day was Monday, February 8, 2016, one day after the HackPoly Hackathon ended. It was back to school after a long and busy weekend. Sadly my team didn’t win, but we ended up making two projects using the Clarifai API. But that’s not the point of this post, the point of this post has to do with my scenario in my Computer Architecture Lab course.

There’s a saying that goes something like this.

When life gives you lemons, you make lemonade.

However, in the world of programming, when things are repetitious, you automate it! In my case, I had to type a 16 line code for a multidimensional array in behavioral Verilog. The task was easy, but tedious.

Ever since I learned about the convenience of Python – being a language that can allow any programmer to create a quick proof of concept – I kind of “fell in love” with the language. To avoid the tedious scenario of typing out 16 lines of somewhat repetitious code, I fired up my Python IDLE, and created a for loop to generate the code needed for my assignment.
for x in range(0, 16):
print("regSlot[" + str(x) + "] = 16'h000" + str(x) + ";")

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Author: Eric Liang

Founder and CEO of Goal Striver

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